A Voltage-Mode Sample and Hold Circuit Based on the Switched Op-Amp Techniques

The design of a simple, fast and accurate sample and hold circuit using a switched op-amp configuration is presented. The unique characteristic of this sample and hold circuit is the cancellation of charge injection effects due to the symmetrical output switched transistors circuit and device configuration. The clock-feed through effect is also reduced by applying the effect of clock pulses to the sources of the main output switched transistors. The circuit is designed using a 2.6 V supply at a clock frequency of 1 MHz. The output error due to an input signal of 1 V peak to peak at frequencies of 20 KHz and 100 KHz is less than 0.25 mV and 0.6mV respectively. Simulation results of second harmonic distortion using 0.25μm CMOS technology at input frequencies of 20 KHZ and 100 KHz is 86 dB and 72.5 dB below the signal level respectively at 1 volt peak to peak input.